1. Field of the Invention
The present invention relates to testing memory arrays and other storage elements embedded inside IC chips at operational/functional speeds.
2. Background Art
Larger memory arrays can be tested with built-in self-test (BIST) engines. BIST engines are expensive in terms of silicon area and typically only justified for larger memory arrays. Many chips have several small embedded memories such as queues, buffers, register files, FIFOs, etc. These array structures are susceptible to defects similar to large arrays, but they are small and the cost of a BIST for such arrays is not justified. In many cases, the BIST engine could be the same size or larger than the array to be tested. In normal operation mode, these arrays can be accessed at GHz frequency ranges. If the reads and writes occur at slow scan test frequencies of a few MHz, several timing related defects are not detected. Scan based manufacturing test of logic built out of combinational gates and flops on a chip is accepted practice today. Since the scan mechanism also provides controllability and observability of nodes deeply embedded in the chip, it can be used to test embedded memory arrays on the chip as well and provide a viable cost alternative to the more expensive BIST.
To test embedded arrays using scan, flops holding data, address and read/write control flops can be scannable so that test data can be written to the array by shifting the data/address value and the write control signal value into a scan chain. After shifting in the data, the functional clock is applied and the data in the flops is written to a correct (tested) address in the array. To read out a test response, the address value and the read control signal value is shifted into the scan chain and a functional clock is applied. After the functional clock is applied, the data read out into the flops is shifted out to be observed and compared to the expected test response. Without any modifications to scan, clocking or the read/write circuits, test data can be written and read from the array as described above at a slow frequency due to the clocks being switched from the slow scan clock to faster functional clock and timed correctly with respect to read and write enablement. In high speed designs, arrays typically use dynamic logic to be able to perform read and write operations at those high speeds. In such dynamic arrays, word lines are pre-charged at a certain polarity in one phase of the functional clock and they get evaluated to the correct value in the other phase of the functional clock. Such arrays pose another problem for high-speed testing using scan because when scan clock is operational, the functional clock is not and hence word lines cannot be in pre-charged state when functional clock is applied after scan shifting.